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intel syntax because at&t just sucks so much to read idek how

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This commit is contained in:
Janis 2024-08-25 16:04:37 +02:00
parent 010e6d2bec
commit c13ed77ddf
1 changed files with 28 additions and 25 deletions
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53
src/triples.rs
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@ -666,7 +666,7 @@ impl core::fmt::Display for RegisterDisplay {
Registers::R15 => "r15", Registers::R15 => "r15",
}; };
write!(f, "%{prefix}{name}{suffix}") write!(f, "{prefix}{name}{suffix}")
} }
} }
@ -744,7 +744,7 @@ impl StackMem {
impl core::fmt::Display for StackMem { impl core::fmt::Display for StackMem {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(f, "-{}(%rbp)", self.offset) write!(f, "[rbp - 0x{:x}]", self.offset)
} }
} }
@ -758,8 +758,8 @@ enum ImmRegMem {
impl core::fmt::Display for ImmRegMem { impl core::fmt::Display for ImmRegMem {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
match self { match self {
ImmRegMem::ImmU32(v) => write!(f, "{v}"), ImmRegMem::ImmU32(v) => write!(f, "0x{v:x}"),
ImmRegMem::ImmU64(v) => write!(f, "{v}"), ImmRegMem::ImmU64(v) => write!(f, "0x{v:x}"),
ImmRegMem::Mem(mem) => write!(f, "{mem}"), ImmRegMem::Mem(mem) => write!(f, "{mem}"),
ImmRegMem::Reg(reg, width) => write!(f, "{}", reg.display(*width)), ImmRegMem::Reg(reg, width) => write!(f, "{}", reg.display(*width)),
} }
@ -783,8 +783,8 @@ impl Function {
writeln!(w, "push {}", reg.display(Width::QWord))?; writeln!(w, "push {}", reg.display(Width::QWord))?;
} }
writeln!(w, "push %rbp")?; writeln!(w, "push rbp")?;
writeln!(w, "mov %rsp, %rbp")?; writeln!(w, "mov rbp, rsp")?;
write!(w, "{}", self.entry)?; write!(w, "{}", self.entry)?;
@ -799,8 +799,8 @@ impl Function {
} }
writeln!(w, "{}__epilogue:", self.name)?; writeln!(w, "{}__epilogue:", self.name)?;
writeln!(w, "mov %rbp, %rsp")?; writeln!(w, "mov rsp, rbp")?;
writeln!(w, "pop %rbp")?; writeln!(w, "pop rbp")?;
for reg in self.used_registers.iter().rev() { for reg in self.used_registers.iter().rev() {
writeln!(w, "pop {}", reg.display(Width::QWord))?; writeln!(w, "pop {}", reg.display(Width::QWord))?;
@ -898,7 +898,7 @@ impl<'a> Assembler<'a> {
let reg = register_store.take_any().unwrap(); let reg = register_store.take_any().unwrap();
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov ${value}, {}", "mov {}, {value}",
reg.display(Width::DWord) reg.display(Width::DWord)
)?; )?;
registers.insert(reg, node); registers.insert(reg, node);
@ -914,7 +914,7 @@ impl<'a> Assembler<'a> {
let reg = register_store.take_any().unwrap(); let reg = register_store.take_any().unwrap();
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov ${value}, {}", "mov {}, {value}",
reg.display(Width::QWord) reg.display(Width::QWord)
)?; )?;
registers.insert(reg, node); registers.insert(reg, node);
@ -933,7 +933,7 @@ impl<'a> Assembler<'a> {
Inst::Alloca => { Inst::Alloca => {
let (size, align) = data.unwrap().as_lhs_rhs(); let (size, align) = data.unwrap().as_lhs_rhs();
let size = size.next_multiple_of(align); let size = size.next_multiple_of(align);
writeln!(&mut func.entry, "sub ${size}, %rsp")?; writeln!(&mut func.entry, "sub rsp, 0x{size:x}")?;
stack_offset += size; stack_offset += size;
allocas.insert(node, stack_offset); allocas.insert(node, stack_offset);
} }
@ -957,27 +957,28 @@ impl<'a> Assembler<'a> {
ImmRegMem::Reg(_, _) => { ImmRegMem::Reg(_, _) => {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov ({}), {}", "mov {}, [{}]",
src,
dst_reg.display(Width::from_size(ty.size()).unwrap()), dst_reg.display(Width::from_size(ty.size()).unwrap()),
src,
)?; )?;
} }
_ => { ImmRegMem::Mem(ref mem) => {
let tmp_reg = register_store.take_any().unwrap(); let tmp_reg = register_store.take_any().unwrap();
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov {}, {}", "mov {}, {}",
src,
tmp_reg.display(Width::QWord), tmp_reg.display(Width::QWord),
mem,
)?; )?;
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov ({}), {}", "mov {}, [{}]",
tmp_reg.display(Width::QWord),
dst_reg.display(Width::from_size(ty.size()).unwrap()), dst_reg.display(Width::from_size(ty.size()).unwrap()),
tmp_reg.display(Width::QWord),
)?; )?;
register_store.free(tmp_reg); register_store.free(tmp_reg);
} }
_ => {}
} }
if let ImmRegMem::Reg(reg, _) = src { if let ImmRegMem::Reg(reg, _) = src {
@ -1015,8 +1016,8 @@ impl<'a> Assembler<'a> {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov {}, {}", "mov {}, {}",
src,
dst, dst,
src,
)?; )?;
if let ImmRegMem::Reg(reg, _) = src { if let ImmRegMem::Reg(reg, _) = src {
@ -1044,8 +1045,8 @@ impl<'a> Assembler<'a> {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"lea {}, {}", "lea {}, {}",
src,
ImmRegMem::Reg(dst_reg, Width::QWord), ImmRegMem::Reg(dst_reg, Width::QWord),
src,
)?; )?;
} }
@ -1053,8 +1054,7 @@ impl<'a> Assembler<'a> {
if offset != 0 { if offset != 0 {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"lea {}({}), {}", "lea {}, [{} + {offset}]",
offset,
ImmRegMem::Reg(dst_reg, Width::QWord), ImmRegMem::Reg(dst_reg, Width::QWord),
ImmRegMem::Reg(dst_reg, Width::QWord), ImmRegMem::Reg(dst_reg, Width::QWord),
)?; )?;
@ -1081,8 +1081,8 @@ impl<'a> Assembler<'a> {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"add {}, {}", "add {}, {}",
src_reg.display(Width::from_size(ty.size()).unwrap()),
dst_reg.display(Width::from_size(ty.size()).unwrap()), dst_reg.display(Width::from_size(ty.size()).unwrap()),
src_reg.display(Width::from_size(ty.size()).unwrap()),
)?; )?;
if src_reg != dst_reg { if src_reg != dst_reg {
@ -1109,8 +1109,8 @@ impl<'a> Assembler<'a> {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"sub {}, {}", "sub {}, {}",
src,
dst_reg.display(Width::from_size(ty.size()).unwrap()), dst_reg.display(Width::from_size(ty.size()).unwrap()),
src,
)?; )?;
if let ImmRegMem::Reg(reg, _) = src { if let ImmRegMem::Reg(reg, _) = src {
@ -1139,8 +1139,8 @@ impl<'a> Assembler<'a> {
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"imul {}, {}", "imul {}, {}",
src,
dst_reg.display(Width::from_size(ty.size()).unwrap()), dst_reg.display(Width::from_size(ty.size()).unwrap()),
src,
)?; )?;
if let ImmRegMem::Reg(reg, _) = src { if let ImmRegMem::Reg(reg, _) = src {
@ -1167,7 +1167,7 @@ impl<'a> Assembler<'a> {
)); ));
writeln!( writeln!(
func.branches.get_mut(&current_branch).unwrap(), func.branches.get_mut(&current_branch).unwrap(),
"mov {}, %rax\njmp {}__epilogue", "mov rax, {}\njmp {}__epilogue",
reg.display(Width::QWord), reg.display(Width::QWord),
func.name func.name
)?; )?;
@ -1210,6 +1210,8 @@ impl<'a> Assembler<'a> {
} }
fn finish<W: core::fmt::Write>(&self, w: &mut W) -> core::fmt::Result { fn finish<W: core::fmt::Write>(&self, w: &mut W) -> core::fmt::Result {
writeln!(w, ".intel_syntax")?;
writeln!(w, ".text")?;
for func in self.functions.iter() { for func in self.functions.iter() {
writeln!(w, ".globl {}", func.name)?; writeln!(w, ".globl {}", func.name)?;
} }
@ -1618,6 +1620,7 @@ impl<'a> MirBuilder<'a> {
mir.gen_ret_val(src) mir.gen_ret_val(src)
} }
Inst::Return => mir.gen_ret(), Inst::Return => mir.gen_ret(),
#[allow(unreachable_patterns)]
_ => { _ => {
unimplemented!() unimplemented!()
} }