boolean arithmetic
This commit is contained in:
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cbc416dcaa
commit
48bbcdec5e
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@ -374,7 +374,7 @@ impl Type {
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Self::Void
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}
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pub fn bool() -> Type {
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Self::Void
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Self::Bool
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}
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pub fn comptime_number() -> Type {
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Self::ComptimeNumber
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275
src/mir.rs
275
src/mir.rs
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@ -1,5 +1,6 @@
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//! Machine-level Intermediate Representation
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use std::cmp::Ordering;
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use std::collections::btree_map::Entry;
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use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet};
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use std::fmt::Display;
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@ -177,6 +178,8 @@ pub enum Inst {
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BitXOr(Type),
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/// lhs
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Negate(Type),
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/// lhs
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Not(Type),
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/// lhs, rhs
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ShiftLeft(Type),
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/// lhs, rhs
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@ -194,6 +197,20 @@ pub enum Inst {
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/// lhs
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IsZero(Type),
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//FunctionStart,
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/// lhs, rhs
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Cmp(Type),
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/// lhs
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IsEq(bool),
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/// lhs
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IsNeq(bool),
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/// lhs
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IsGt(bool),
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/// lhs
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IsLt(bool),
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/// lhs
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IsGe(bool),
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/// lhs
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IsLe(bool),
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}
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impl Inst {
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@ -211,6 +228,7 @@ impl Inst {
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| Inst::ConstantQWord
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| Inst::ConstantSinglePrecision
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| Inst::ConstantDoublePrecision
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| Inst::Cmp(_)
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| Inst::Return => None,
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Inst::GetElementPtr(ty)
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| Inst::Load(ty)
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@ -231,12 +249,19 @@ impl Inst {
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| Inst::BitOr(ty)
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| Inst::BitXOr(ty)
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| Inst::Negate(ty)
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| Inst::Not(ty)
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| Inst::SignExtend(ty)
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| Inst::ZeroExtend(ty)
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| Inst::ShiftLeft(ty)
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| Inst::ShiftRightSigned(ty)
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| Inst::ShiftRightUnsigned(ty) => Some(*ty),
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Inst::IsZero(_) => Some(Type::Byte),
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Inst::IsZero(_)
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| Inst::IsEq(_)
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| Inst::IsNeq(_)
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| Inst::IsGt(_)
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| Inst::IsLt(_)
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| Inst::IsGe(_)
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| Inst::IsLe(_) => Some(Type::Byte),
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}
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}
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#[allow(dead_code)]
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@ -256,6 +281,7 @@ impl Inst {
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| Inst::Alloca
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| Inst::Store(_)
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| Inst::ReturnValue(_)
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| Inst::Cmp(_)
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| Inst::Return => false,
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Inst::GetElementPtr(_)
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| Inst::Load(_)
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@ -276,9 +302,16 @@ impl Inst {
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| Inst::BitOr(_)
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| Inst::BitXOr(_)
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| Inst::Negate(_)
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| Inst::Not(_)
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| Inst::SignExtend(_)
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| Inst::ZeroExtend(_)
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| Inst::IsZero(_)
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| Inst::IsEq(_)
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| Inst::IsNeq(_)
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| Inst::IsGt(_)
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| Inst::IsLt(_)
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| Inst::IsGe(_)
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| Inst::IsLe(_)
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| Inst::ShiftLeft(_)
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| Inst::ShiftRightSigned(_)
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| Inst::ShiftRightUnsigned(_) => true,
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@ -412,7 +445,7 @@ bitflags! {
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}
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impl OperandKinds {
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/// works for: add,sub,or,and,sbb,adc
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/// works for: add,sub,or,and,sbb,adc,cmp
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fn add() -> Self {
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Self::RegImm | Self::MemImm | Self::RegMem | Self::MemReg | Self::RegReg
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}
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@ -625,7 +658,7 @@ impl<'a> BinaryOperands<'a> {
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fn new_add_or_and_xor_adc(mir: &'a mut Mir) -> Self {
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Self::new(mir, true, OperandKinds::add())
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}
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fn new_sub_sbb(mir: &'a mut Mir) -> Self {
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fn new_sub_sbb_cmp(mir: &'a mut Mir) -> Self {
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Self::new(mir, false, OperandKinds::add())
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}
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fn new_sse(mir: &'a mut Mir) -> Self {
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@ -753,46 +786,7 @@ impl Mir {
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}
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pub fn is_register(&self, node: u32) -> bool {
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match self.nodes[node as usize] {
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Inst::LoadRegister(_)
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| Inst::Load(_)
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| Inst::GetElementPtr(_)
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| Inst::Parameter(_)
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| Inst::Add(_)
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| Inst::Sub(_)
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| Inst::Mul(_)
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| Inst::MulSigned(_)
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| Inst::Div(_)
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| Inst::DivSigned(_)
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| Inst::Rem(_)
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| Inst::RemSigned(_)
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| Inst::MulSSE(_)
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| Inst::DivSSE(_)
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| Inst::RemFP(_)
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| Inst::BitAnd(_)
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| Inst::BitOr(_)
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| Inst::BitXOr(_)
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| Inst::Negate(_)
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| Inst::SignExtend(_)
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| Inst::ZeroExtend(_)
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| Inst::IsZero(_)
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| Inst::ShiftLeft(_)
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| Inst::ShiftRightSigned(_)
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| Inst::ShiftRightUnsigned(_) => true,
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Inst::Label
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| Inst::ConstantBytes
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| Inst::ConstantByte
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| Inst::ConstantWord
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| Inst::ConstantDWord
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| Inst::ConstantQWord
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| Inst::ConstantSinglePrecision
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| Inst::ConstantDoublePrecision
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| Inst::ExternRef
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| Inst::Alloca
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| Inst::Store(_)
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| Inst::ReturnValue(_)
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| Inst::Return => false,
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}
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self.nodes[node as usize].result_is_register()
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}
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pub fn is_imm(&self, node: u32) -> bool {
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@ -842,6 +836,73 @@ impl Mir {
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pub fn gen_is_zero(&mut self, ty: Type, src: u32) -> u32 {
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self.push(Inst::IsZero(ty), Data::node(src))
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}
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pub fn gen_cmp(&mut self, ty: Type, lhs: u32, rhs: u32) -> u32 {
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let (lhs, rhs) = if ty.is_floating() {
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BinaryOperands::new_sse(self).wrangle(lhs, ty, rhs, ty)
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} else {
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BinaryOperands::new_sub_sbb_cmp(self).wrangle(lhs, ty, rhs, ty)
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};
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self.push(Inst::Cmp(ty), Data::binary(lhs, rhs))
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}
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pub fn gen_cmp_byte(
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&mut self,
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ty: Type,
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signed: bool,
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ordering: Ordering,
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invert: bool,
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lhs: u32,
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rhs: u32,
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) -> u32 {
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match ordering {
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Ordering::Less => {
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if invert {
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self.gen_is_ge(ty, signed, lhs, rhs)
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} else {
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self.gen_is_lt(ty, signed, lhs, rhs)
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}
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}
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Ordering::Equal => {
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if invert {
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self.gen_is_neq(ty, signed, lhs, rhs)
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} else {
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self.gen_is_eq(ty, signed, lhs, rhs)
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}
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}
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Ordering::Greater => {
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if invert {
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self.gen_is_le(ty, signed, lhs, rhs)
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} else {
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self.gen_is_gt(ty, signed, lhs, rhs)
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}
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}
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}
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}
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pub fn gen_is_eq(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsEq(signed), Data::node(cmp))
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}
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pub fn gen_is_neq(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsNeq(signed), Data::node(cmp))
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}
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pub fn gen_is_gt(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsGt(signed), Data::node(cmp))
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}
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pub fn gen_is_lt(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsLt(signed), Data::node(cmp))
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}
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pub fn gen_is_ge(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsGe(signed), Data::node(cmp))
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}
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pub fn gen_is_le(&mut self, ty: Type, signed: bool, lhs: u32, rhs: u32) -> u32 {
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let cmp = self.gen_cmp(ty, lhs, rhs);
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self.push(Inst::IsLe(signed), Data::node(cmp))
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}
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pub fn gen_load_register(&mut self, ty: Type, src: u32) -> u32 {
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self.push(Inst::LoadRegister(ty), Data::node(src))
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}
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@ -910,7 +971,7 @@ impl Mir {
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// 1111_1111 << 4 = 1111_0000
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// mask = 0000_1111;
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// shift = 8 - 4;
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let src_ty = self.type_of_node(src).unwrap();
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let src_ty = Type::from_bitsize_int(from.bits as u32);
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let truncated = self.gen_truncate_integer(src, src_ty, from.signed, from.bits);
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let dst_ty = Type::from_bitsize_int(to.bits as u32);
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@ -942,7 +1003,7 @@ impl Mir {
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let (lhs, rhs) = if ty.is_floating() {
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BinaryOperands::new_sse(self).wrangle(lhs, ty, rhs, ty)
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} else {
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BinaryOperands::new_sub_sbb(self).wrangle(lhs, ty, rhs, ty)
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BinaryOperands::new_sub_sbb_cmp(self).wrangle(lhs, ty, rhs, ty)
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};
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self.push(Inst::Sub(ty), Data::binary(lhs, rhs))
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}
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@ -1027,6 +1088,10 @@ impl Mir {
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let src = self.imm_to_reg(src);
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self.push(Inst::Negate(ty), Data::node(src))
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}
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pub fn gen_not(&mut self, ty: Type, src: u32) -> u32 {
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let src = self.imm_to_reg(src);
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self.push(Inst::Not(ty), Data::node(src))
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}
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#[doc(alias = "gen_shift_left")]
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pub fn gen_shl(&mut self, ty: Type, src: u32, shift: u32) -> u32 {
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@ -1171,6 +1236,10 @@ impl Mir {
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let lhs = data.as_node();
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writeln!(w, "%{node} = negate {ty} %{lhs}")
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}
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Inst::Not(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = bitwise not {ty} %{lhs}")
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}
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Inst::SignExtend(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = sign extend {ty} %{lhs}")
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@ -1183,6 +1252,34 @@ impl Mir {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is zero {ty} %{lhs}")
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}
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Inst::Cmp(ty) => {
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let (lhs, rhs) = data.as_binary();
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writeln!(w, "%{node} = cmp {ty} %{lhs} {ty} %{rhs}")
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}
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Inst::IsEq(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is eq %{lhs}")
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}
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Inst::IsNeq(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is neq %{lhs}")
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}
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Inst::IsGt(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is gt %{lhs}")
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}
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Inst::IsLt(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is lt %{lhs}")
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}
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Inst::IsGe(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is ge %{lhs}")
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}
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Inst::IsLe(ty) => {
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let lhs = data.as_node();
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writeln!(w, "%{node} = is le %{lhs}")
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}
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Inst::ShiftLeft(ty) => {
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let (lhs, rhs) = data.as_binary();
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writeln!(w, "%{node} = shift left {ty} %{lhs}, {ty} %{rhs}")
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@ -1445,12 +1542,20 @@ pub mod liveness {
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| Inst::SignExtend(_)
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| Inst::ZeroExtend(_)
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| Inst::Negate(_)
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| Inst::Not(_)
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| Inst::IsZero(_)
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| Inst::IsEq(_)
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| Inst::IsNeq(_)
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| Inst::IsGt(_)
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| Inst::IsGe(_)
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| Inst::IsLt(_)
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| Inst::IsLe(_)
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| Inst::Load(_)
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| Inst::LoadRegister(_) => {
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references.insert((data.as_noderef(), node));
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}
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Inst::Store(_)
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Inst::Cmp(_)
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| Inst::Store(_)
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| Inst::Add(_)
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| Inst::Sub(_)
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| Inst::Mul(_)
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@ -1641,7 +1746,7 @@ impl Mir {
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let (lhs, _) = data.as_binary_noderefs();
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Some(lhs)
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}
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Inst::Negate(_) => {
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Inst::Not(_) | Inst::Negate(_) => {
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let lhs = data.as_noderef();
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Some(lhs)
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}
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@ -1670,6 +1775,13 @@ impl Mir {
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| Inst::DivSigned(_)
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| Inst::Rem(_)
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| Inst::RemSigned(_)
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| Inst::Cmp(_)
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| Inst::IsEq(_)
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| Inst::IsNeq(_)
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| Inst::IsGt(_)
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| Inst::IsLt(_)
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| Inst::IsGe(_)
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| Inst::IsLe(_)
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| Inst::IsZero(_) => None,
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}
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}
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@ -1978,6 +2090,7 @@ impl Mir {
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| Inst::BitOr(ty)
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| Inst::BitXOr(ty)
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| Inst::Negate(ty)
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| Inst::Not(ty)
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| Inst::ShiftLeft(ty)
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| Inst::ShiftRightSigned(ty)
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| Inst::ShiftRightUnsigned(ty)
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@ -1988,6 +2101,16 @@ impl Mir {
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| Inst::LoadRegister(ty) => ty
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.register_width(liveness.get_register(node.into()).unwrap())
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.into(),
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Inst::IsEq(_)
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| Inst::IsGt(_)
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| Inst::IsLt(_)
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| Inst::IsGe(_)
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| Inst::IsLe(_)
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| Inst::IsNeq(_) => liveness
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.get_register(node.into())
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.unwrap()
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.into_byte()
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.into(),
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Inst::Alloca => {
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let (offset, size) = *mapping.get(&(node as usize)).unwrap();
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ImmRegMem::Mem(StackMem::new(offset, size))
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@ -2775,6 +2898,16 @@ impl Mir {
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writeln!(func.current_branch(), "mov {dst}, {lhs}")?;
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}
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}
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Inst::Not(ty) => {
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let dst = ty.register_width(liveness.get_register(node.into()).unwrap());
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let lhs = data.as_node();
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let lhs = self.node_as_operand(&liveness, &mapping, &mut func, strings, lhs);
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writeln!(func.current_branch(), "not {lhs}")?;
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if !lhs.occupy_same_register(dst) {
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writeln!(func.current_branch(), "mov {dst}, {lhs}")?;
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}
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}
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Inst::Negate(ty) => {
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let dst = ty.register_width(liveness.get_register(node.into()).unwrap());
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let lhs = data.as_node();
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@ -2904,6 +3037,38 @@ impl Mir {
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}
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}
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}
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Inst::Cmp(ty) => {
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let (lhs, rhs) = data.as_binary();
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let lhs = self.node_as_operand(&liveness, &mapping, &mut func, strings, lhs);
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let rhs = self.node_as_operand(&liveness, &mapping, &mut func, strings, rhs);
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if ty.is_floating() {
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writeln!(func.current_branch(), "comiss {lhs}, {rhs}")?;
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} else {
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writeln!(func.current_branch(), "cmp {lhs}, {rhs}")?;
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}
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}
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Inst::IsEq(signed)
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| Inst::IsNeq(signed)
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| Inst::IsGt(signed)
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| Inst::IsLt(signed)
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| Inst::IsGe(signed)
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| Inst::IsLe(signed) => {
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let dst = liveness.get_register(node.into()).unwrap().into_byte();
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#[cfg_attr(rustfmt, rustfmt::skip)]
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let mnemonic = match inst {
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Inst::IsEq(_) => "sete",
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Inst::IsNeq(_) => "setne",
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Inst::IsGt(_) => if signed {"setg"} else {"seta"},
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Inst::IsLt(_) => if signed {"setl"} else {"setb"},
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Inst::IsGe(_) => if signed {"setge"} else {"setae"},
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Inst::IsLe(_) => if signed {"setle"} else {"setbe"},
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
writeln!(func.current_branch(), "{mnemonic} {dst}")?;
|
||||
}
|
||||
Inst::IsZero(ty) => {
|
||||
let dst = ty.register_width(liveness.get_register(node.into()).unwrap());
|
||||
let lhs = data.as_node();
|
||||
|
|
@ -2916,13 +3081,17 @@ impl Mir {
|
|||
let lhs = data.as_node();
|
||||
let lhs = self.node_as_operand(&liveness, &mapping, &mut func, strings, lhs);
|
||||
if ty.is_floating() {
|
||||
writeln!(func.current_branch(), "movss xmm0, {lhs}",)?;
|
||||
if !lhs.occupy_same_register(Register::xmm0) {
|
||||
writeln!(func.current_branch(), "movss xmm0, {lhs}",)?;
|
||||
}
|
||||
} else {
|
||||
writeln!(
|
||||
func.current_branch(),
|
||||
"mov {}, {lhs}",
|
||||
Register::rax.into_bytesize(lhs.byte_width())
|
||||
)?;
|
||||
if !lhs.occupy_same_register(Register::rax) {
|
||||
writeln!(
|
||||
func.current_branch(),
|
||||
"mov {}, {lhs}",
|
||||
Register::rax.into_bytesize(lhs.byte_width())
|
||||
)?;
|
||||
}
|
||||
}
|
||||
writeln!(func.current_branch(), "jmp {name}__epilogue")?;
|
||||
}
|
||||
|
|
|
|||
129
src/triples.rs
129
src/triples.rs
|
|
@ -1,6 +1,9 @@
|
|||
#![allow(dead_code)]
|
||||
|
||||
use std::collections::{hash_map::Entry, BTreeMap, BTreeSet, HashMap};
|
||||
use std::{
|
||||
cmp::Ordering,
|
||||
collections::{hash_map::Entry, BTreeMap, BTreeSet, HashMap},
|
||||
};
|
||||
|
||||
use crate::{
|
||||
ast::{IntegralType, Node as AstNode, Tag, Type},
|
||||
|
|
@ -154,6 +157,20 @@ pub enum Inst {
|
|||
/// lhs
|
||||
Negate(Type2),
|
||||
/// lhs
|
||||
Not(Type2),
|
||||
/// lhs, rhs
|
||||
Eq(Type2),
|
||||
/// lhs, rhs
|
||||
Neq(Type2),
|
||||
/// lhs, rhs
|
||||
Gt(Type2),
|
||||
/// lhs, rhs
|
||||
Lt(Type2),
|
||||
/// lhs, rhs
|
||||
Ge(Type2),
|
||||
/// lhs, rhs
|
||||
Le(Type2),
|
||||
/// lhs
|
||||
ExplicitCast(Type2, Type2),
|
||||
/// lhs
|
||||
ReturnValue(Type2),
|
||||
|
|
@ -290,7 +307,8 @@ impl<'tree, 'ir> IRBuilder<'tree, 'ir> {
|
|||
}
|
||||
|
||||
fn visit(&mut self, node: AstNode) -> Node {
|
||||
match &self.tree.nodes[node].clone() {
|
||||
let tag = &self.tree.nodes[node].clone();
|
||||
match tag {
|
||||
Tag::FunctionDecl { proto, body } => {
|
||||
variant!(
|
||||
Tag::FunctionProto {
|
||||
|
|
@ -424,6 +442,36 @@ impl<'tree, 'ir> IRBuilder<'tree, 'ir> {
|
|||
self.ir
|
||||
.push(Inst::BitXOr(ty.into()), Some(Data::new(lhs, rhs)))
|
||||
}
|
||||
Tag::Lt { lhs, rhs }
|
||||
| Tag::Ge { lhs, rhs }
|
||||
| Tag::Le { lhs, rhs }
|
||||
| Tag::Eq { lhs, rhs }
|
||||
| Tag::NEq { lhs, rhs }
|
||||
| Tag::Gt { lhs, rhs } => {
|
||||
let ty = self
|
||||
.tree
|
||||
.peer_type_of_nodes(*lhs, *rhs)
|
||||
.expect({
|
||||
let at = self.tree.type_of_node(*lhs);
|
||||
let bt = self.tree.type_of_node(*rhs);
|
||||
&format!("incompatible types for %{lhs}({at}) and %{rhs}({bt})")
|
||||
})
|
||||
.into();
|
||||
|
||||
let inst = match tag {
|
||||
Tag::Eq { .. } => Inst::Eq(ty),
|
||||
Tag::NEq { .. } => Inst::Neq(ty),
|
||||
Tag::Gt { .. } => Inst::Gt(ty),
|
||||
Tag::Lt { .. } => Inst::Lt(ty),
|
||||
Tag::Ge { .. } => Inst::Ge(ty),
|
||||
Tag::Le { .. } => Inst::Le(ty),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
let lhs = self.visit(*lhs);
|
||||
let rhs = self.visit(*rhs);
|
||||
self.ir.push(inst, Some(Data::new(lhs, rhs)))
|
||||
}
|
||||
Tag::Mul { lhs, rhs } => {
|
||||
let ty = self.tree.type_of_node(node);
|
||||
let lhs = self.visit(*lhs);
|
||||
|
|
@ -436,6 +484,11 @@ impl<'tree, 'ir> IRBuilder<'tree, 'ir> {
|
|||
let lhs = self.visit(*lhs);
|
||||
self.ir.push(Inst::Negate(ty.into()), Some(Data::lhs(lhs)))
|
||||
}
|
||||
Tag::Not { lhs } => {
|
||||
let ty = self.tree.type_of_node(node);
|
||||
let lhs = self.visit(*lhs);
|
||||
self.ir.push(Inst::Not(ty.into()), Some(Data::lhs(lhs)))
|
||||
}
|
||||
Tag::Shl { lhs, rhs } => {
|
||||
let ty = self.tree.type_of_node(node);
|
||||
let lhs = self.visit(*lhs);
|
||||
|
|
@ -578,6 +631,30 @@ impl<'tree, 'ir> IRBuilder<'tree, 'ir> {
|
|||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = sub_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Eq(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = eq_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Neq(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = neq_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Gt(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = gt_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Lt(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = lt_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Ge(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = ge_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Le(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = le_{ty}(%{} - %{})", node, lhs, rhs)?;
|
||||
}
|
||||
Inst::Mul(ty) => {
|
||||
let (lhs, rhs) = data.as_lhs_rhs();
|
||||
writeln_indented!(indent, w, "%{} = mul_{ty}(%{} * %{})", node, lhs, rhs)?;
|
||||
|
|
@ -585,6 +662,9 @@ impl<'tree, 'ir> IRBuilder<'tree, 'ir> {
|
|||
Inst::Negate(ty) => {
|
||||
writeln_indented!(indent, w, "%{} = negate_{ty}(%{})", node, data.lhs)?;
|
||||
}
|
||||
Inst::Not(ty) => {
|
||||
writeln_indented!(indent, w, "%{} = bitwise_not_{ty}(%{})", node, data.lhs)?;
|
||||
}
|
||||
Inst::ExplicitCast(from, to) => {
|
||||
writeln_indented!(indent, w, "%{} = cast_{from}_to_{to}(%{})", node, data.lhs)?;
|
||||
}
|
||||
|
|
@ -1170,6 +1250,12 @@ impl<'a> Assembler<'a> {
|
|||
allocas.insert(node, stack_offset);
|
||||
registers.insert(param_reg, node);
|
||||
}
|
||||
Inst::Eq(ty)
|
||||
| Inst::Neq(ty)
|
||||
| Inst::Gt(ty)
|
||||
| Inst::Lt(ty)
|
||||
| Inst::Ge(ty)
|
||||
| Inst::Le(ty) => {}
|
||||
Inst::Add(ty) => {
|
||||
let (src, dst) = data.unwrap().as_lhs_rhs();
|
||||
let (&src_reg, _) = registers.iter().find(|(_, node)| node == &&src).unwrap();
|
||||
|
|
@ -1255,6 +1341,7 @@ impl<'a> Assembler<'a> {
|
|||
Inst::BitOr(_) => todo!(),
|
||||
Inst::BitXOr(_) => todo!(),
|
||||
Inst::Negate(_) => todo!(),
|
||||
Inst::Not(_) => todo!(),
|
||||
Inst::ExplicitCast(_, _) => todo!(),
|
||||
Inst::ReturnValue(_) => {
|
||||
let val = data.unwrap().lhs;
|
||||
|
|
@ -1411,6 +1498,29 @@ impl<'a> MirBuilder<'a> {
|
|||
// let (size, _) = data.unwrap().as_lhs_rhs();
|
||||
mir.gen_param(ty.into())
|
||||
}
|
||||
Inst::Eq(ty)
|
||||
| Inst::Neq(ty)
|
||||
| Inst::Gt(ty)
|
||||
| Inst::Lt(ty)
|
||||
| Inst::Ge(ty)
|
||||
| Inst::Le(ty) => {
|
||||
let (src, dst) = data.unwrap().as_lhs_rhs();
|
||||
let lhs = *mapping.get(&src).unwrap();
|
||||
let rhs = *mapping.get(&dst).unwrap();
|
||||
|
||||
#[cfg_attr(rustfmt, rustfmt::skip)]
|
||||
let (ord, invert)= match inst {
|
||||
Inst::Eq(_) => (Ordering::Equal, false),
|
||||
Inst::Neq(_) => (Ordering::Equal, true),
|
||||
Inst::Gt(_) => (Ordering::Greater, false),
|
||||
Inst::Le(_) => (Ordering::Greater, true),
|
||||
Inst::Lt(_) => (Ordering::Less, false),
|
||||
Inst::Ge(_) => (Ordering::Less, true),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
mir.gen_cmp_byte(ty.mir_type(), ty.is_signed(), ord, invert, lhs, rhs)
|
||||
}
|
||||
Inst::Add(ty) => {
|
||||
let (src, dst) = data.unwrap().as_lhs_rhs();
|
||||
let lhs = *mapping.get(&src).unwrap();
|
||||
|
|
@ -1629,6 +1739,21 @@ impl<'a> MirBuilder<'a> {
|
|||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
Inst::Not(ty) => {
|
||||
let lhs = data.unwrap().as_u32();
|
||||
|
||||
let unalignment = ty.mir_unalignment();
|
||||
let ty = ty.mir_type();
|
||||
|
||||
let lhs = *mapping.get(&lhs).unwrap();
|
||||
|
||||
let sum = mir.gen_not(ty, lhs);
|
||||
if let Some((signed, bits)) = unalignment {
|
||||
mir.gen_truncate_integer(sum, ty, signed, bits)
|
||||
} else {
|
||||
sum
|
||||
}
|
||||
}
|
||||
Inst::Negate(ty) => {
|
||||
let lhs = data.unwrap().as_u32();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue